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mc145170-2 ordering information device operating temp range package mc145170p2 t a = -40 to 85c plastic dip MC145170D2 sog-16 mc145170dt2 tssop-16 p suffix case 648 dt suffix case 948c d suffix case 751b ? motorola, inc., 2003. all rights reserved. 1 introduction the new mc145170-2 is pin-for-pin compatible with the mc145170-1. a comparison of the two parts is shown in the table below. the mc145170-2 is recommended for new designs and has a more robust power-on reset (por) circuit that is more responsive to momentary power supply interruptions. the two devices are actually the same chip with mask options for the por circuit. the more robust por circuit draws approximately 20 a additional supply current. note that the maximum specification of 100 a quiescent supply current has not changed. the mc145170-2 is a single-chip synthesizer capable of direct usage in the mf, hf, and vhf bands. a special architecture makes this pll easy to program. either a bit- or byte- oriented format may be used. due to the patented bitgrabber ? registers, no address/steering bits are required for random access of the three registers. thus, tuning can be accomplished via a 2-byte serial transfer to the 16-bit n register. the device features fully programmable r and n counters, an amplifier at the f in pin, on-chip support of an external crystal, a programmable reference output, and both single- and double- ended phase detectors with linear transfer functions (no dead zones). a configuration (c) register allows the part to be configured to meet various applications. a patented feature allows the c register to shut off unused outputs, thereby minimizing noise and interference. in order to reduce lock times and prevent erroneous data from being loaded into the counters, a patented jam-load feature is included. whenever a new divide ratio is loaded into the n register, both the n and r counters are jam-loaded with their respective values and begin counting down together. the phase detectors are also initialized during the jam load. ? operating voltage range: 2.7 to 5.5 v technical data mc145170-2/d rev. 4, 02/2003 pll frequency synthesizer with serial interface contents : 1 introduction . . . . . . . . . . 1 2 specifications . . . . . . . . 3 3 pin connections . . . . . 10 4 design considerations 18 5 packaging. . . . . . . . . . . 30 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2 mc145170-2 technical data motorola introduction ? maximum operating frequency: 185 mhz @ v in = 500 mvpp, 4.5 v minimum supply 100 mhz @ v in = 500 mvpp, 3.0 v minimum supply ? operating supply current: 0.6 ma @ 3.0 v, 30 mhz 1.5 ma @ 3.0 v, 100 mhz 3.0 ma @ 5.0 v, 50 mhz 5.8 ma @ 5.0 v, 185 mhz ? operating temperature range: -40 to 85 c ? r counter division range: 1 and 5 to 32,767 ? n counter division range: 40 to 65,535 ? direct interface to motorola spi serial data port ? see application notes an1207/d and an1671/d ? contact motorola for mc145170 control software. table 1. comparision of the pll frequency synthesizers parameter mc145170-2 mc145170-1 minimum supply voltage 2.7 v 2.5 v maximum input current, f in 150 a 120 a dynamic characteristics, f in (figure 26) unchanged - power-on reset circuit improved - f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical characteristics motorola mc145170-2 technical data 3 figure 1. block diagram 2 electrical characteristics table 2. maximum ratings (voltages referenced to v ss ) parameter symbol value unit dc supply voltage v dd -0.5 to 5.5 v dc input voltage v in -0.5 to v dd + 0.5 v dc output voltage v out -0.5 to v dd + 0.5 v dc input current, per pin i in 10 ma dc output current, per pin i out 20 ma dc supply current, v dd and v ss pins i dd 30 ma power dissipation, per package p d 300 mw storage temperature t stg -65 to 150 c lead temperature, 1 mm from case for 10 seconds t l 260 c notes: 1. maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the limits in the electrical characteristics tables or pin descriptions section. 2. esd data available upon request. bitgrabber r register 15 bits lock detector and control bitgrabber c register 8 bits phase/frequency detector a and control por phase/frequency detector b and control bitgrabber n register 16 bits osc shift register and control logic enb osc in d in clk osc out f in 1 2 7 5 4 3 15 16 16 ld pd out f r f v 10 15 14 13 11 9 pin 16 = v dd pin 12 = v ss input amp 6 4-stage reference divider ref out 3 dout 8 f v control f r f v 15-stage r counter f r control 16-stage n counter this device contains 4,800 active transistors. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4 mc145170-2 technical data motorola electrical characteristics table 3. electrical characteristics (voltages referenced to v ss , t a = -40 to 85 c) parameter test condition symbol v dd v guaranteed limit unit power supply voltage range v dd - 2.7 to 5.5 v maximum low-level input voltage [note 1] (d in , clk, enb , f in ) dc coupling to f in v il 2.7 4.5 5.5 0.54 1.35 1.65 v minimum high-level input voltage [note 1] (d in , clk, enb , f in ) dc coupling to f in v ih 2.7 4.5 5.5 2.16 3.15 3.85 v minimum hysteresis voltage (clk, enb ) v hys 2.7 5.5 0.15 0.20 v maximum low-level output voltage (any output) i out = 20 a v ol 2.7 5.5 0.1 0.1 v minimum high-level output voltage (any output) i out = - 20 a v oh 2.7 5.5 2.6 5.4 v minimum low-level output current (pd out , ref out , f r , f v , ld, r , v ) v out = 0.3 v v out = 0.4 v v out = 0.5 v i ol 2.7 4.5 5.5 0.12 0.36 0.36 ma minimum high-level output current (pd out , ref out , f r , f v , ld, r , v ) v out = 2.4 v v out = 4.1 v v out = 5.0 v i oh 2.7 4.5 5.5 -0.12 -0.36 -0.36 ma minimum low-level output current (d out ) v out = 0.4 v i ol 4.5 1.6 ma minimum high-level output current (d out ) v out = 4.1 v i oh 4.5 -1.6 ma maximum input leakage current (d in , clk, enb , osc in ) v in = v dd or v ss i in 5.5 1.0 a maximum input current (f in ) v in = v dd or v ss i in 5.5 150 a maximum output leakage current (pd out ) (d out ) v in = v dd or v ss , output in high-impedance state i oz 5.5 5.5 100 5.0 na a maximum quiescent supply current v in = v dd or v ss ; outputs open; excluding f in amp input current component i dd 5.5 100 a notes: 1. when dc coupling to the osc in pin is used, the pin must be driven rail-to-rail. in this case, osc out should be floated. 2. the nominal values at 3.0 v are 0.6 ma @ 30 mhz, and 1.5 ma @ 100 mhz. the nominal values at 5.0 v are 3.0 ma @ 50 mhz, and 5.8 ma @ 185 mhz. these are not guaranteed limits. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical characteristics motorola mc145170-2 technical data 5 maximum operating supply current f in = 500 mvpp; osc in = 1.0 mhz @ 1.0 vpp; ld, f r , f v , ref out = inactive and no connect; osc out , v , r , pd out = no connect; d in , enb, clk = v dd or v ss i dd - [note 2] ma table 4. ac interface characteristics ( t a = -40 to 85c, c l = 50 pf, input tr = t f = 10 ns, unless otherwise noted.) parameter symbol figure no. v dd v guaranteed limit unit serial data clock frequency (note: refer to clock t w below) f clk 22.7 4.5 5.5 dc to 3.0 dc to 4.0 dc to 4.0 mhz maximum propagation delay, clk to d out t plh , t phl 2, 6 2.7 4.5 5.5 150 85 85 ns maximum disable time, d out active to high impedance t plz , t phz 3, 7 2.7 4.5 5.5 300 200 200 ns access time, d out high impedance to active t pzl , t pzh 3, 7 2.7 4.5 5.5 0 to 200 0 to 100 0 to 100 ns maximum output transition time, d out cl = 50 pf t tlh , t thl 2, 6 2.7 4.5 5.5 150 50 50 ns cl = 200 pf 2, 6 2.7 4.5 5.5 900 150 150 ns maximum input capacitance - d in , enb , clk c in -10pf maximum output capacitance - d out c out -10pf table 3. electrical characteristics (continued) (voltages referenced to v ss , t a = -40 to 85 c) parameter test condition symbol v dd v guaranteed limit unit notes: 1. when dc coupling to the osc in pin is used, the pin must be driven rail-to-rail. in this case, osc out should be floated. 2. the nominal values at 3.0 v are 0.6 ma @ 30 mhz, and 1.5 ma @ 100 mhz. the nominal values at 5.0 v are 3.0 ma @ 50 mhz, and 5.8 ma @ 185 mhz. these are not guaranteed limits. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6 mc145170-2 technical data motorola electrical characteristics table 5. timing requirements (t a = -40 to 85c, input t r = t f = 10 ns, unless otherwise noted.) parameter symbol figure no. v dd v guaranteed limit unit minimum setup and hold times, d in vs clk t su , t h 42.7 4.5 5.5 55 40 40 ns minimum setup, hold, and recovery times, enb vs clk t su , t h , t rec 52.7 4.5 5.5 135 100 100 ns minimum inactive-high pulse width, enb t w(h) 52.7 4.5 5.5 400 300 300 ns minimum pulse width, clk t w 22.7 4.5 5.5 166 125 125 ns maximum input rise and fall times, clk t r , t f 22.7 4.5 5.5 100 100 100 s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical characteristics motorola mc145170-2 technical data 7 2.1 switching waveforms figure 2. figure 3. figure 4. figure 5. figure 6. test circuit figure 7. test circuit 10% v dd v ss 1/fclk d out clk 90% 50% 90% 50% 10% t plh t phl t tlh t thl t w t w t f t r enb d out d out 50% v dd v ss 50% t pzh t pzl t plz 50% t phz 10% 90% v dd v ss high impedance high impedance d in clk 50% valid 50% t su t h v dd v ss v dd v ss clk enb 50% t su t h first clk last clk t rec 50% v dd v ss v dd v ss t w(h) * includes all probe and fixture capacitance. test point device under test cl* test point device under test cl* *includes all probe and fixture capacitance. 7.5 k ? connect to v dd when testing t plz and t pzl . connect to v ss when testing t phz and t pzh . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8 mc145170-2 technical data motorola electrical characteristics table 6. loop specifications (t a = -40 to 85c) parameter test condition symbol figure no. v dd v guaranteed range unit min max input frequency, f in [note} v in 500 mvpp sine wave, n counter set to divide ratio such that f v 2.0 mhz f82.7 3.0 4.5 5.5 5.0 5.0 25 45 80 100 185 185 mhz input frequency, osc in externally driven with ac-coupled signal v in 1.0 v pp sine wave, osc out = no connect, r counter set to divide ratio such that f r 2 mhz f92.7 3.0 4.5 5.5 1.0* 1.0* 1.0* 1.0* 22 25 30 35 mhz crystal frequency, osc in and osc out c1 30 pf c2 30 pf includes stray capacitance f xtal 11 2.7 3.0 4.5 5.5 2.0 2.0 2.0 2.0 12 12 15 15 mhz output frequency, ref out c l = 30 pf f out 12, 14 2.7 4.5 5.5 dc dc dc - 10 10 mhz operating frequency of the phase detectors f2.7 4.5 5.5 dc dc dc - 2.0 2.0 mhz output pulse width, r , v , and ld f r in phase with f v c l = 50 pf t w 13, 14 2.7 4.5 5.5 - 20 16 - 100 90 ns output transition times, r , v , ld, f r , and f v c l = 50 pf t tlh , t thl 13, 14 2.7 4.5 5.5 - - - - 65 60 ns input capacitance f in osc in c in - - - - - - 7.0 7.0 pf * if lower frequency is desired, use wave shaping or higher amplitude sinusoidal signal in ac-coupled case. also, see figure 25 for dc coupling. figure 8. test circuit, f in sine wave generator 100 pf mc145170-2 test point v+ v dd f in f v v in 50 ? * v ss *characteristic impedance f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
electrical characteristics motorola mc145170-2 technical data 9 figure 9. test circuit, osc circuitry externally driven [note] figure 10. circuit to eliminate self-oscillation, osc circuitry externally driven [note] note: use the circuit of figure 10 to eliminate self-oscillation of the oscin pin when the mc145170-2 has power applied with no external signal applied at vin. (self-oscillation is not harmful to the mc145170-2 and does not damage the ic.) figure 11. test circuit, osc circuit with crystal figure 12. test circuit figure 13. switching waveform figure 14. test load circuit sine wave generator 50 ? 0.01 f test point v dd osc in f r v in v+ v ss mc145170-2 osc out 5.0 m ? sine wave generator 50 ? 0.01 f test point v dd osc in f r v in v+ v ss mc145170-2 osc out v+ 1.0 m ? no connect 1.0 m ? c1 test point v dd ref out v ss osc in osc out c2 v+ mc145170-2 50% refout 1/f ref out 10% 90% output t tlh t thl 50% t w test point device under test cl* *includes all probe and fixture capacitance. output f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
10 mc145170-2 technical data motorola pin connections 3 pin connections 3.1 digital interface pins d in serial data input (pin 5) the bit stream begins with the most significant bit (msb) and is shifted in on the low-to-high transition of clk. the bit pattern is 1 byte (8 bits) long to access the c or configuration register, 2 bytes (16 bits) to access the n register, or 3 bytes (24 bits) to access the r register. additionally, the r register can be accessed with a 15-bit transfer (see table 7). an optional pattern which resets the device is shown in figure 15. the values in the c, n, and r registers do not change during shifting because the transfer of data to the registers is controlled by enb . the bit stream needs neither address nor steering bits due to the innovative bitgrabber registers. therefore, all bits in the stream are available to be data for the three registers. random access of any register is provided (i.e., the registers may be accessed in any sequence). data is retained in the registers over a supply range of 2.7 to 5.5 v. the formats are shown in figures 15, 16, 17, and 18. d in typically switches near 50% of v dd to maximize noise immunity. this input can be directly interfaced to cmos devices with outputs guaranteed to switch near rail-to-rail. when interfacing to nmos or ttl devices, either a level shifter (mc74hc14a, mc14504b) or pull-up resistor of 1 to 10 k ? must be used. parameters to consider when sizing the resistor are worst-case i ol of the driving device, maximum tolerable power consumption, and maximum data rate. clk serial data clock input (pin 7) low-to-high transitions on clock shift bits available at d in , while high-to-low transitions shift bits from d out . the chip's 16-1/2-stage shift register is static, allowing clock rates down to dc in a continuous or intermittent mode. four to eight clock cycles followed by five clock cycles are needed to reset the device; this is optional. eight clock cycles are required to access the c register. sixteen clock cycles are needed for the n register. either 15 or 24 cycles can be used to access the r register (see table 7 and figures 15, 16, 17, and 18). for cascaded devices, see figures 27 to 34 . clk typically switches near 50% of v dd and has a schmitt-triggered input buffer. slow clk rise and fall times are allowed. see the last paragraph of d in for more information. note: to guarantee proper operation of the power-on reset (por) circuit, the clk pin must be held at the potential of either the v ss or v dd pin during power up. that is, the clk input should not be floated or toggled while the v dd pin is ramping from 0 to at least 2.7 v. if control of the clk pin is not practical during power up, the initialization sequence shown in figure 15 must be used. table 7. register access (msbs are shifted in first, c0, n0, and r0 are the lsbs) number of clocks accessed register bit nomenclature 9 to 13 8 16 15 or 24 other values 32 values > 32 see figure 15 c register n register r register none see figures 27 to 34 (reset) c7, c6, c5, ..., c0 n15, n14, n13, ..., n0 r14, r13, r12, ..., r0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pin connections motorola mc145170-2 technical data 11 enb active-low enable input (pin 6) this pin is used to activate the serial interface to allow the transfer of data to/from the device. when enb is in an inactive high state, shifting is inhibited, d out is forced to the high-impedance state, and the port is held in the initialized state. to transfer data to the device, enb (which must start inactive high) is taken low, a serial transfer is made via din and clk, and enb is taken back high. the low-to-high transition on enb transfers data to the c, n, or r register depending on the data stream length per table 7. note: transitions on enb must not be attempted while clk is high. this puts the device out of synchronization with the microcontroller. resynchronization occurs when enb is high and clk is low. this input is also schmitt-triggered and switches near 50% of v dd , thereby minimizing the chance of loading erroneous data into the registers. see the last paragraph of d in for more information. d out three-state serial data output (pin 8) data is transferred out of the 16-1/2-stage shift register through dout on the high-to-low transition of clk. this output is a no connect, unless used in one of the manners discussed below. dout could be fed back to an mcu/mpu to perform a wrap-around test of serial data. this could be part of a system check conducted at power up to test the integrity of the system's processor, pc board traces, solder joints, etc. the pin could be monitored at an in-line qa test during board manufacturing. finally, d out facilitates troubleshooting a system and permits cascading devices. 3.2 reference pins osc in /osc out reference oscillator input/output (pins 1, 2) these pins form a reference oscillator when connected to terminals of an external parallel-resonant crystal. frequency-setting capacitors of appropriate values as recommended by the crystal supplier are connected from each pin to ground (up to a maximum of 30 pf each, including stray capacitance). an external feedback resistor of 1.0 to 5.0 m ? is connected directly across the pins to ensure linear operation of the amplifier. the required connections for the components are shown in figure 11. 5 m ? is required across the osc in and osc out pins in the ac-coupled case (see figure 9 or alternate circuit figure 10). osc out is an internal node on the device and should not be used to drive any loads (i.e., osc out is unbuffered). however, the buffered ref out is available to drive external loads. the external signal level must be at least 1 vpp; the maximum frequencies are given in the loop specifications table. these maximum frequencies apply for r counter divide ratios as indicated in the table. for very small ratios, the maximum frequency is limited to the divide ratio times 2 mhz. (reason: the phase/frequency detectors are limited to a maximum input frequency of 2 mhz.) if an external source is available which swings virtually rail-to-rail (v dd to v ss ), then dc coupling can be used. in the dc-coupled case, no external feedback resistor is needed. osc out must be a no connect to avoid loading an internal node on the device, as noted above. for frequencies below 1 mhz, dc coupling must be used. the r counter is a static counter and may be operated down to dc. however, wave shaping by a cmos buffer may be required to ensure fast rise and fall times into the osc in pin. see figure 25. each rising edge on the osc in pin causes the r counter to decrement by one. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
12 mc145170-2 technical data motorola pin connections ref out reference frequency output (pin 3) this output is the buffered output of the crystal-generated reference frequency or externally provided reference source. this output may be enabled, disabled, or scaled via bits in the c register (see figure 16). ref out can be used to drive a microprocessor clock input, thereby saving a crystal. upon power up, the on- chip power-on-initialize circuit forces ref out to the osc in divided-by-8 mode. ref out is capable of operation to 10 mhz; see the loop specifications table. therefore, divide values for the reference divider are restricted to two or higher for osc in frequencies above 10 mhz. if unused, the pin should be floated and should be disabled via the c register to minimize dynamic power consumption and electromagnetic interference (emi). 3.3 counter output pins f r r counter output (pin 9) this signal is the buffered output of the 15-stage r counter. f r can be enabled or disabled via the c register (patented). the output is disabled (static low logic level) upon power up. if unused, the output should be left disabled and unconnected to minimize interference with external circuitry. the f r signal can be used to verify the r counter's divide ratio. this ratio extends from 5 to 32,767 and is determined by the binary value loaded into the r register. also, direct access to the phase detector via the osc in pin is allowed by choosing a divide value of 1 (see figure 17). the maximum frequency which the phase detectors operate is 2 mhz. therefore, the frequency of f r must not exceed 2 mhz. when activated, the f r signal appears as normally low and pulses high. the pulse width is 4.5 cycles of the osc in pin signal, except when a divide ratio of 1 is selected. when 1 is selected, the osc in signal is buffered and appears at the f r pin. f v n counter output (pin 10) this signal is the buffered output of the 16-stage n counter. f v can be enabled or disabled via the c register (patented). the output is disabled (static low logic level) upon power up. if unused, the output should be left disabled and unconnected to minimize interference with external circuitry. the f v signal can be used to verify the n counter's divide ratio. this ratio extends from 40 to 65,535 and is determined by the binary value loaded into the n register. the maximum frequency which the phase detectors operate is 2 mhz. therefore, the frequency of f v must not exceed 2 mhz. when activated, the f v signal appears as normally low and pulses high. 3.4 loop pins f in frequency input (pin 4) this pin is a frequency input from the vco. this pin feeds the on-chip amplifier which drives the n counter. this signal is normally sourced from an external voltage-controlled oscillator (vco), and is ac- coupled into f in . a 100 pf coupling capacitor is used for measurement purposes and is the minimum size recommended for applications (see figure 25). the frequency capability of this input is dependent on the supply voltage as listed in table 6, loop specifications. for small divide ratios, the maximum frequency is limited to the divide ratio times 2 mhz. (reason: the phase/frequency detectors are limited to a maximum frequency of 2 mhz.) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pin connections motorola mc145170-2 technical data 13 for signals which swing from at least the v il to v ih levels listed in the electrical characteristics table, dc coupling may be used. also, for low frequency signals (less than the minimum frequencies shown in the loop specifications table), dc coupling is a requirement. the n counter is a static counter and may be operated down to dc. however, wave shaping by a cmos buffer may be required to ensure fast rise and fall times into the f in pin. see figure 25. each rising edge on the f in pin causes the n counter to decrement by 1. pd out single-ended phase/frequency detector output (pin 13) this is a three-state output for use as a loop error signal when combined with an external low-pass filter. through use of a motorola patented technique, the detector's dead zone has been eliminated. therefore, the phase/frequency detector is characterized by a linear transfer function. the operation of the phase/ frequency detector is described below and is shown in figure 19. pol bit (c7) in the c register = low (see figure 16) frequency of f v > f r or phase of f v leading f r : negative pulses from high impedance frequency of f v < f r or phase of f v lagging f r : positive pulses from high impedance frequency and phase of f v = f r : essentially high-impedance state; voltage at pin determined by loop filter pol bit (c7) = high frequency of f v > f r or phase of f v leading f r : positive pulses from high impedance frequency of f v < f r or phase of f v lagging f r : negative pulses from high impedance frequency and phase of f v = f r : essentially high-impedance state; voltage at pin determined by loop filter this output can be enabled, disabled, and inverted via the c register. if desired, pd out can be forced to the high-impedance state by utilization of the disable feature in the c register (patented). r and v double-ended phase/frequency detector outputs (pins 14, 15) these outputs can be combined externally to generate a loop error signal. through use of a motorola patented technique, the detector's dead zone has been eliminated. therefore, the phase/frequency detector is characterized by a linear transfer function. the operation of the phase/frequency detector is described below and is shown in figure 19. pol bit (c7) in the c register = low (see figure 16) frequency of f v > f r or phase of f v leading f r : v = negative pulses, r = essentially high frequency of f v < f r or phase of f v lagging f r : v = essentially high, r = negative pulses frequency and phase of f v = f r : v and r remain essentially high, except for a small minimum time period when both pulse low in phase pol bit (c7) = high frequency of f v > f r or phase of f v leading f r : r = negative pulses, v = essentially high frequency of f v < f r or phase of f v lagging f r : r = essentially high, v = negative pulses frequency and phase of f v = f r : v and r remain essentially high, except for a small minimum time period when both pulse low in phase these outputs can be enabled, disabled, and interchanged via the c register (patented). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14 mc145170-2 technical data motorola pin connections ld lock detector output (pin 11) this output is essentially at a high level with narrow low-going pulses when the loop is locked (f r and f v of the same phase and frequency). the output pulses low when f v and f r are out of phase or different frequencies (see figure 19). this output can be enabled and disabled via the c register (patented). upon power up, on-chip initialization circuitry disables ld to a static low logic level to prevent a false lock signal. if unused, ld should be disabled and left open. 3.5 power supply v dd most positive supply potential (pin 16) this pin may range from 2.7 to 5.5 v with respect to v ss . for optimum performance, v dd should be bypassed to v ss using low-inductance capacitor(s) mounted very close to the device. lead lengths on the capacitor(s) should be minimized. (the very fast switching speed of the device causes current spikes on the power leads.) v ss most negative supply potential (pin 12) this pin is usually ground. for measurement purposes, the v ss pin is tied to a ground plane. figure 15. reset sequence enb clk d in power up 123 4 or more clocks 5 1234 don't cares don't cares one zeroes zero note: this initialization sequence is usually not necessary because the on-chip power-on reset circuit performs the initialization function. however, this initialization sequence must be used immediately after power up if control of the clk pin is not possible. that is, if clk (pin 7) toggl es or floats upon power up, use the above sequence to reset the device. also, use this sequence if powe r is momentarily interrupted such that the supply voltage to the device is reduced to below 2.7 v, but not down to at least 1 v (for example, the supply drops down to 2 v). this is necessary because the on-chip power-on reset is only activat ed when the supply ramps up from a voltage below approximately 1.0 v. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pin connections motorola mc145170-2 technical data 15 figure 16. c register access and format (8 clock cycles are used) enb clk d in msb lsb c7 c6 c5 c4 c3 c2 c1 c0 1 234 5678 * * at this point, the new byte is transferred to the c register and stored. no other registers are affected. c7 - pol: select the output polarity of the phase/frequency detectors. when set high, this bit inverts pd out and interchanges the r function with v as depicted in figure 19. also see the phase detector output pin descriptions for more information. this bit is cleared low at power up. c6 - pda/b: selects which phase/frequency detector is to be used. when set high, enables the output of phase/frequency detector a (pd out ) and disables phase/frequency detector b by forcing r and v to the static high state. when cleared low, phase/frequency detector b is enabled ( r and v ) and phase/frequency detector a is disabled with pd out forced to the high-impedance state. this bit is cleared low at power up. c5 - lde: enables the lock detector output when set high. when the bit is cleared low, the ld output is forced to a static low level. this bit is cleared low at power up. c4 - c2, osc2 - osc0: reference output controls which determines the ref out characteristics as shown below. upon power up, the bits are initialized such that osc in /8 is selected. c1 - f v e: enables the f v output when set high. when cleared low, the f v output is forced to a static low level. the bit is cleared low upon power up. c0 - f r e: enables the f r output when set high. when cleared low, the f r output is forced to a static low level. the bit is cleared low upon power up. c4 c3 c2 ref out frequency 0 0 0 dc (static low) 001osc in 010osc in /2 011osc in /4 100osc in /8 (por default) 101osc in /16 110osc in /8 111osc in /16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16 mc145170-2 technical data motorola pin connections figure 17. r register access and formats (either 24 or 15 clock cycles can be used) x x x x x x x x r 1 4 r 1 3 r 1 2 r 1 1 r 1 0 r 9 r 8 r 7 r 6 r 5 r 4 r 3 r 2 r 1 r 0 x 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 1 m s b l s b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 n o t a l l o w e d r c o u n t e r = 1 ( d i r e c t a c c e s s t o r e f e r e n c e s i d e o f p h a s e / f r e q u e n c y d e t e c t o r ) n o t a l l o w e d n o t a l l o w e d n o t a l l o w e d r c o u n t e r = 5 r c o u n t e r = 6 r c o u n t e r = 7 . . . f f . . . f f . . . e f r c o u n t e r = 3 2 , 7 6 6 r c o u n t e r = 3 2 , 7 6 7 h e x a d e c i m a l v a l u e l k n 0 0 0 0 0 0 0 0 . . . 7 7 d o n ' t c a r e b i t s s e e b e l o w s e e b e l o w s e e b e l o w s e e b e l o w r 1 4 r 1 3 r 1 2 r 1 1 r 1 0 r 9 r 8 r 7 r 6 r 5 r 4 r 3 r 2 r 1 r 0 l s b 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 m s b o c t a l v a l u e d e c i m a l e q u i v a l e n t e n b c l k d i n * * * a t t h i s p o i n t , t h e n e w d a t a i s t r a n s f e r r e d t o t h e r r e g i s t e r a n d s t o r e d . n o o t h e r r e g i s t e r s a r e a f f e c t e d . n b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pin connections motorola mc145170-2 technical data 17 figure 18. n register access and format (16 clock cycles are used) figure 19. phase/frequency detector and lock detector output waveforms enb clk d in 12345678 msb lsb n10n9n8n7n6n5n4n3n2n1n0 n11 n12 n13 n14 n15 9 10111213141516 0 0 0 0 0 0 0 0 0 0 0 f f 0 0 0 0 2 2 2 2 2 2 2 f f 0 1 2 3 5 6 7 8 9 a b e f not allowed not allowed not allowed not allowed not allowed not allowed not allowed n counter = 40 n counter = 41 n counter = 42 n counter = 43 n counter = 65,534 n counter = 65,535 hexadecimal value 0 0 0 0 0 0 0 0 0 0 0 f f decimal equivalent * . . . . . . . . .. .. . . . . . . . . .. .. *at this point, the two new bytes are trans ferred to the n register and stored. no ot her registers are affected. in addition, t he n and r counters are jam-loaded and begin counting down together. f r reference osc in r f v feedback (f in n pd out r v ld v h v l v h v h v h v l high impedance v h v l v l v l v h v l * v h = high voltage level v l = low voltage level *at this point, when both f r and f v are in phase, both the sinking and sourcing output fets are turned on for a very short internal. note: the pd out generates error pulses during out-of-lock conditions. when locked in phase and frequency, the output is high impedance and the voltage at that pin is determi ned by the low-pass filter capacitor. pdout, r and v are shown with the polarity bit (pol) = low; see figure 16 for pol. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18 mc145170-2 technical data motorola design considerations 4 design considerations 4.1 crystal oscillator considerations the following options may be considered to provide a reference frequency to motorola's cmos frequency synthesizers. 4.1.1 use of a hybrid crystal oscillator commercially available temperature-compensated crystal oscillators (tcxos) or crystal-controlled data clock oscillators provide very stable reference frequencies. an oscillator capable of cmos logic levels at the output may be direct or dc coupled to osc in . if the oscillator does not have cmos logic levels on the outputs, capacitive or ac coupling to osc in may be used (see figures 9 and 10). for additional information about tcxos, visit motorola.com on the world wide web. 4.1.2 use of the on-chip oscillator circuitry the on-chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source frequency. a fundamental mode crystal, parallel resonant at the desired operating frequency, should be connected as shown in figure 20. the crystal should be specified for a loading capacitance (c l ) which does not exceed 20 pf when used at the highest operating frequencies listed in table 6, loop specifications . larger c l values are possible for lower frequencies. assuming r1 = 0 ? , the shunt load capacitance (c l ) presented across the crystal can be estimated to be: where c in = 5.0 pf (see figure 21) c out = 6.0 pf (see figure 21) c a = 1.0 pf (see figure 21) c1 and c2 = external capacitors (see figure 21) c stray = the total equivalent external circuit stray capacitance appearing across the crystal terminals the oscillator can be trimmed on-frequency by making a portion or all of c1 variable. the crystal and associated components must be located as close as possible to the osc in and osc out pins to minimize distortion, stray capacitance, stray inductance, and startup stabilization time. circuit stray capacitance can also be handled by adding the appropriate stray value to the values for c in and c out . for this approach, the term c stray becomes 0 in the above expression for c l . a good design practice is to pick a small value for c1, such as 5 to 10 pf. next, c2 is calculated. c1 < c2 results in a more robust circuit for start-up and is more tolerant of crystal parameter variations. power is dissipated in the effective series resistance of the crystal, r e , in figure 22. the maximum drive level specified by the crystal manufacturer represents the maximum stress that the crystal can withstand without damage or excessive shift in operating frequency. r1 in figure 20. limits the drive level. the use of r1 is not necessary in most cases. c l c in c out c in c out + ----------------------------- c a c stray c1 c2 c1 c2 + ---------------------- ++ + = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
design considerations motorola mc145170-2 technical data 19 to verify that the maximum dc supply voltage does not cause the crystal to be overdriven, monitor the output frequency at the ref out pin (osc out is not used because loading impacts the oscillator). the frequency should increase very slightly as the dc supply voltage is increased. an overdriven crystal decreases in frequency or becomes unstable with an increase in supply voltage. the operating supply voltage must be reduced or r1 must be increased in value if the overdriven condition exists. the user should note that the oscillator start-up time is proportional to the value of r1. through the process of supplying crystals for use with cmos inverters, many crystal manufacturers have developed expertise in cmos oscillator design with crystals. discussions with such manufacturers can prove very helpful (see table 8). figure 20. pierce crystal oscillator circuit figure 21. parasitic capacitances of the amplifier and c stray figure 22. equivalent crystal networks r1* c2 c1 frequency synthesizer osc out osc in r f * may be needed in certain cases. see text. 5.0 to 10 pf c in c out c a osc in osc out c stray 2 1 2 1 2 1 rs ls cs re xe co note: values are supplied by crystal manufacturer (parallel resonant crystal). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
20 mc145170-2 technical data motorola design considerations recommended reading technical note tn-24, statek corp. technical note tn-7, statek corp. e. hafner, the piezoelectric crystal unit-definitions and method of measurement, proc. ieee, vol. 57, no. 2, feb. 1969. d. kemper, l. rosine, quartz crystals for frequency control, electro-technology , june 1969. p. j. ottowitz, a guide to crystal selection, electronic design , may 1966. d. babin, designing crystal oscillators, machine design , march 7, 1985. d. babin, guidelines for crystal oscillator design, machine design , april 25, 1985. contact motorola for mc145170-2 control software. table 8. partial list of crystal manufacturers cts corp. united states crystal corp. crystek crystal statek corp. fox electronics note: motorola cannot recommend one supplier over another and in no way suggests that this is a complete listing of crystal manufacturers. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
design considerations motorola mc145170-2 technical data 21 figure 23. phase-locked loop - low pass filter design c vco pd out r 1 c vco r 2 pd out r 1 a c r 2 c vco r v r 1 - + mc33077 or equivalent (note 3) r 1 r 2 (a) (b) (c) n k k vco nr 1 c ------------------------- = n n 2k k vco ----------------------------- - = fs () 1 r 1 sc 1 + ------------------------- - = n k k vco nc r 1 r 2 + () ------------------------------------ = 0.5 n r 2 c n k k vco ------------------------- + ?? ?? ?? = fs () r 2 sc 1 + r 1 r 2 + () sc 1 + -------------------------------------------- - = n k k vco ncr 1 ------------------------- = n r 2 c 2 -------------------- = fs () r 2 sc 1 + r 1 sc ------------------------- - = notes: 1. for (c), r 1 is frequently split into two series resistors; each resistor is equal to r 1 divided by 2. a capacitor c c is then placed from the midpoint to ground to further filter the error pulses. the value of c c should be such that the corner frequency of this network does not significantly affect n . 2. the r and v outputs swing rail-to-rail. therefore, the user should be careful not to exceed the common mode input range of the op amp. 3. for the latest information on mc33077 or equivalent, see the motorola ic web site at http://www.motorola.com/semiconductors . denifitions: n = total division ratio in feedback loop k (phase detector gain) = vdd/4p volts per radian for pdout k (phase detector gain) - vdd/2p volts per radian for fv and fr for a nominal design starting point, the user might consider a damping factor = 0.7 and a natural loop frequency n = (2 f r /50) where f r is the frequency at the phase detector input. larger n values result in faster loop lock times and, for similar sideband filtering, higher f r -related vco standards. k vco vco gain () 2 ? f vco ? v vco -------------------------- = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
22 mc145170-2 technical data motorola design considerations figure 24. example application mcu threshold detector osc in v dd f in osc out v r v ss f r ld enb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vhf output buffer optional ref d in d out pd out v+ integrator vhf vco low-pass filter v+ optional loop error signals (note 1) m c 1 4 5 1 7 0 - 2 clk f v optional (note 5) (note 4) notes: 1. the r and v outputs are fed to an external combiner/l oop filter. see the phase-locked loop low-pass filter design page for additional information. the r and v outputs swing rail-to-rail. therefore, the user should be careful not to exceed the common mode input range of the op amp used inthe combiner/loop filter. 2. for optimum performance, bypass the v dd pin to v ss (gnd) with one or more low-inductance capacitors. 3. the r counter is programmed for a divide value = osc in /f r . typically, f r is the tuning resolution required for the vco. also, the vco frequency divided by f r = n, wher e n is the divide value of the n counter. 4. may be an r-c low-pass filter. 5. may be a bipolar transistor. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
design considerations motorola mc145170-2 technical data 23 figure 25. low frequency operation using dc coupling osc in f in osc out v ss v+ c d a b no connect mc74hc14a mc145170-2 v dd 2 4 1 3 14 7 note: the signals at points a and b may be low-frequency sinusoidal or square waves with slow edge rates or noisy signal edges. at points c and d, the signals are cleaned up, have sharp edge rates, and rail-to-rail signal swings. with signals as described at points c and d, the mc145170-2 is guaranteed to operate down to a frequency as low as dc. refer to the mc74hc14a data sheet for input switching levels and hysteresis voltage range. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
24 mc145170-2 technical data motorola design considerations figure 26. input impedance at f in - series format (r + jx) (5.0 mhz to 185 mhz) figure 27. cascading two mc145170-2 devices 4 3 2 1 f in (pin 4) sog package marker frequency (mhz) resistance ( ? ) reactance ( ? ) capacitance (pf) 1 5 2390 -5900 5.39 2 100 39.2 -347 4.58 3 150 25.8 -237 4.48 4 185 42.6 -180 4.79 device #1 mc145170-2 cmos mcu optional d out enb clk d in device #2 mc145170-2 enb clk d in d out 33 k ? note 1 notes: 1. the 33 k ? resistor is needed to prevent the d in pin from floating. (the d out pin is a three-state output.) 2. see related figures 28 , 29 , and 30. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
25 mc145170-2 technical data motorola figure 28. accessing the c registers of two cascaded mc145170-2 devices figure 29. accessing the r registers of two cascaded mc145170-2 devices note: at this point, the new data is transferred to the c regist ers of both devices and stored. no other registers are affected . 1 2 7 8 9 1 0 1 5 1 6 1 7 1 8 2 3 2 4 2 5 2 6 3 1 3 2 3 3 3 4 3 9 4 0 c r e g i s t e r b i t s o f d e v i c e # 2 i n f i g u r e 2 7 c r e g i s t e r b i t s o f d e v i c e # 1 i n f i g u r e 2 7 x x x x x x c 7 c 6 c 0 x x x c 7 c 6 c 0 e n b c l k d i n n o t e note: at this point, the new data is transferred to the r regist ers of both devices and stored. no other registers are affected . e n b c l k d i n 1 2 8 9 1 0 2 5 2 6 2 7 3 0 3 1 3 9 4 0 4 1 4 2 4 4 4 5 r r e g i s t e r b i t s o f d e v i c e # 2 i n f i g u r e 2 7 r r e g i s t e r b i t s o f d e v i c e # 1 i n f i g u r e 2 7 x x x x r 1 4 r 1 3 x r 1 4 r 1 1 4 8 4 9 5 0 5 5 5 6 r 7 r 6 r 0 r 0 r 1 r 9 n o t e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
26 mc145170-2 technical data motorola figure 30. accessing the n registers of two cascaded mc145170-2 devices note: at this point, the new data is transferred to the n regist ers of both devices and stored. no other registers are affected . 1 2 8 9 1 0 1 5 1 6 1 7 2 3 2 4 2 5 3 1 3 2 3 3 n r e g i s t e r b i t s o f d e v i c e # 2 i n f i g u r e 2 7 n r e g i s t e r b i t s o f d e v i c e # 1 i n f i g u r e 2 7 x x x x x n 1 5 n 8 n 7 n 0 n 1 5 3 9 4 0 4 1 4 7 4 8 n 8 n 7 n 0 e n b c l k d i n n o t e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
design considerations motorola mc145170-2 technical data 27 figure 31. cascading two different device types v dd device #1 mc145170-2 cmos mcu optional d out enb clk d in device #2 note 2 enb clk d in output a (d out ) 33 k ? note 1 v pd v pd v cc v dd v+ notes: 1. the 33 k ? resistor is needed to prevent the d in pin from floating. (the d out pin is a three-state output.) 2. this pll frequency synthesizer may be a mc145190, mc145191, mc145192, mc145200, or mc145201. 3. see related figures 32, 33, and 34. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
28 mc145170-2 technical data motorola figure 32. accessing the c registers of two different device types figure 33. accessing the a and r registers of two different device types note: at this point, the new data is transferred to the c regist ers of both devices and stored. no other registers are affected . 1 2 7 8 9 1 0 1 5 1 6 1 7 1 8 2 3 2 4 2 5 2 6 3 1 3 2 3 3 3 4 3 9 4 0 c r e g i s t e r b i t s o f d e v i c e # 2 i n f i g u r e 3 1 c r e g i s t e r b i t s o f d e v i c e # 1 i n f i g u r e 3 1 x x x x x x c 7 c 6 c 0 x x x c 7 c 6 c 0 e n b c l k d i n n o t e note: at this point, the new data is transferred to the a register of device #2 and r register of device #1 and stored. no othe r registers are affected. e n b c l k d i n 1 2 1 6 1 7 1 8 2 0 2 1 2 2 3 0 3 1 3 2 3 9 4 0 4 1 4 2 4 3 a r e g i s t e r b i t s o f d e v i c e # 2 i n f i g u r e 3 1 r r e g i s t e r b i t s o f d e v i c e # 1 i n f i g u r e 3 1 x x a 2 3 a 2 2 a 1 9 a 1 8 a 0 x 4 6 4 7 4 8 5 5 5 6 r 9 r 8 r 0 a 8 r 1 4 r 1 3 a 9 n o t e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
29 mc145170-2 technical data motorola figure 34. accessing the r and n registers of two different device types note: at this point, the new data is transferred to the r regist er of device #2 and n register of device #1 and stored. no othe r registers are affected. 1 2 8 9 1 0 1 5 1 6 1 7 2 3 2 4 2 5 3 1 3 2 3 3 r r e g i s t e r b i t s o f d e v i c e # 2 i n f i g u r e 3 1 n r e g i s t e r b i t s o f d e v i c e # 1 i n f i g u r e 3 1 x x x x x r 1 5 r 8 r 7 r 0 n 1 5 3 9 4 0 4 1 4 7 4 8 n 8 n 7 n 0 e n b c l k d i n n o t e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
30 mc145170-2 technical data motorola packaging 5 packaging figure 35. outline dimensions for p suffix, dip-16 (case 648-08, issue r) figure 36. outline dimensions for d suffix, sog-16 (case 751b-05, issue j) -a- b f c s h g d 16 pl j l m seating plane 18 9 16 k -t- m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 010 010 s 0.020 0.040 0.51 1.01 _ _ _ _ notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. seating plane 0.49 16x b m 0.25 a t 0.35 1.75 1.35 0.25 0.10 6 t 16x 0.1 t 1.27 14x 7 1.25 0.40 0 0.25 0.19 section a-a notes: 1. dimensions are in millimeters. 2. dimensioning and tolerancing per asme y14.5m, 1994. 3. datums a and b to be determined at the plane where the bottom of the leads exit the plastic body. 4. this dimension does not include mold flash, protrusion or gate burrs, mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side. this dimension is determined at the plane where the bottom of the leads exit the plastic body. 5. this dimension does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25 mm per side. this dimension is determined at the plane where the bottom of the leads exit the plastic body. 6. this dimension does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed 0.62 mm. 89 116 8x 6.2 5.8 m 0.25 b 4 10.0 9.8 a 4.0 3.8 b pin 1 index pin's number a a 5 0.50 x45 0.25 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
packaging motorola mc145170-2 technical data 31 figure 37. outline dimensions for dt suffix, tssop-16 (case 948c-03, issue b) dim min max min max inches millimeters a --- 5.10 --- 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0047 d 0.05 0.25 0.002 0.010 f 0.45 0.55 0.018 0.022 g 0.65 bsc 0.026 bsc h 0.22 0.23 0.009 0.010 j 0.09 0.24 0.004 0.009 k 0.16 0.32 0.006 0.013 l 6.30 6.50 0.248 0.256 m 010 010 55 55 j1 0.09 0.18 0.004 0.007 k1 0.16 0.26 0.006 0.010 a b pin 1 identification l 18 9 16 16x ref k m 0.200 (0.008) t -p- d c seating g h m 0.100 (0.004) plane -t- -u- f m a a k k1 j j1 section a-a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimensions a and b are to be determined at datum plane -u-. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145170-2/d how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd.; sps, technical information center, 3-20-1, minami-azabu minato-ku, tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: 1-800-521-6274 home page: http://www.motorola.com/semiconductors information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer application by customers technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark office. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 2003 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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